Synthesis ramstyle

I just wanted to post an answer here for future reference. I was having exactly the same issue and it took me a while to find the answer so hopefully this reply will help someone.

The tools do in fact support inferring an MLAB with an asynchronous read. The original posters logic is precisely correct, however, they are missing one little key piece of info that the synthesis tool needs in order to allow the inference to occur. The syn_ramstyle attribute must be slightly modified to include the "no_rw_check" option as follows:

/* synthesis syn_ramstyle = "MLAB, no_rw_check"*/

This will allow the tool to properly infer the dual-port MLAB with asynchronous read. If you do not add the "no_rw_check" attribute then you will receive the following message from MAP:

Info (276009): RAM logic is uninferred due to unsupported read-during-write behavior

Here is the official Altera answer if anyone is interested in the details:

https://www.altera.com/servlets/searchredirect?srtitle=how_to_infer_mlab_with_asynchronous_read&contactid=1-7ifaal&resulttitle=can%20quartus%20ii%20synthesis%20%3cb%3einfer%3c/b%3e%20a%20small%20%3cb%3easynchronous%3c/b%3e%20memory%20%3cb%3e...%3c/b%3e&resulturl=http://www.altera.com/support/kdb/solutions/rd12112006_212.html&gsa_pos=1&wt.oss_r=1&wt.oss=how%20to%20infer%20mlab%20with%20asynchronous%20read&srno=11067666

The "no_rw_check" syn_ramstyle attribute is not required if the user is trying to infer a synchronous read. In fact, you should make sure that you don't include it in order to avoid hardware/simulation mismatches.