Synthesis ramstyle

I'm not using Veriolg, but I hope, the synthesis attributes (you're actually using it twice) should work. I also noticed that Stratix IV is supporting asynchronous read (I assume, you are not using Stratix V, that is yet unsupported by available Quartus versions ...). The Quartus Verilog templates are suggesting a slightly different syntax, however.

The RAM inference templates don't have an synchronous read example. It may be the case, that this mode isn't supported for interference. You may want to use an explicite MegaFunction instance instead of spending much time with trial-and-error.