Syntax error in defining Heirarchy.. System Verilog

I have my enum type defined as:

typedef enum {
chain_master,
A_master,
B_master,
ip1_slave,
ip2_slave,
master,
slave
} ip_chain;

I have a heirarchy which i have defined as following:

`define heirarchy_tree 
begin 
tree.master=chain_master; 
tree.master=chain_master; 
tree.master=chain_master; 
tree.master=A_master; 
tree.master=B_master; 
end

When I compile it, I get the syntax error:

Syntax error:

token is 'tree'

tree[chain_master].master=chain_master;

Can anyone tell what is missing?