syncronous clocks

Another related question: when using clock enables to clock data at a slower rate than the system clock I know you can use timing constraints to let the router know that this path can have reduced timing requirements for the data being transfered between registers. However, the clock enable signal must still meet the faster system clock timing requirements. If I use timing constraints for the multi-cycle paths does the Quartus software only apply them to the data path and not the clock enable path?