Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorsyncronous clocks
This may seem a like a stupid question, but I am new to Altera FPGA's. When using a PLL to generate syncronous clocks, lets say a base clock and a base clock multipled by 2 for example, can I assume ...
Altera_ForumHonored Contributor
Honored ContributorAnother related question: when using clock enables to clock data at a slower rate than the system clock I know you can use timing constraints to let the router know that this path can have reduced timing requirements for the data being transfered between registers. However, the clock enable signal must still meet the faster system clock timing requirements. If I use timing constraints for the multi-cycle paths does the Quartus software only apply them to the data path and not the clock enable path?
P.S. Thanks for all the replies, they have helped me to understand the details of designing with Altera FPGA's
