Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorsyncronous clocks
This may seem a like a stupid question, but I am new to Altera FPGA's. When using a PLL to generate syncronous clocks, lets say a base clock and a base clock multipled by 2 for example, can I assume ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- As you said, an enable signal is better than multiple clk system if that is feasible. --- Quote End --- The systems base clock is choosen usually in a tradeoff between speed requirements and allowed logic or arithmetic complexety. It typically doesn't allow a double speed without adding considerably more pipeline levels. Auxilary slower clocks can be most easily created as divider generated clock enables rather than additional PLL clocks. Faster clocks, e.g. to drive memory interfaces or serial IO need PLL outputs in contrast. Their relation to the main clock when crossing the domains is always considered correctly by the Quartus timing analysis, as far as I experienced.
