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As you said, an enable signal is better than multiple clk system if that is feasible.
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The systems base clock is choosen usually in a tradeoff between speed requirements and allowed logic or arithmetic complexety. It typically doesn't allow a double speed without adding considerably more pipeline levels. Auxilary slower clocks can be most easily created as divider generated clock enables rather than additional PLL clocks. Faster clocks, e.g. to drive memory interfaces or serial IO need PLL outputs in contrast. Their relation to the main clock when crossing the domains is always considered correctly by the Quartus timing analysis, as far as I experienced.
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