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Unfortunately the system is composed by two different fpgas with 2 different clocks' sources because the fpgas are located on 2 independent boards. The sync pulses come from an external cpu (another board in the system).
I'd like the idea of PLL but i don't know how to implement it....
The simplest way for me in order to avoid heavy changes on alredy written code is acting on NCO inputs.
Have you any ideas?
Thanks
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For two untied clocks(clk1 & clk2) it is not doable in principle unless you have some signal from one clk to other clock domain.
Your sync pulse must be 20ns (not 10ns) and may be it is generated in clk1 domain. In this case you might be able to apply your PLL to count time in between pulses (nominally 100ms) in clk2 domain.
As I said you can then use an accumulator that adds up this counter value to generate an enable pulse that can be ANDed with you clock enable on NCO2.
for example if it counted less then clk2 is slower so increase your enable rate on NCO2 and vice versa. keep NCO1 as it is. You will also need to cross clock domain carefully and a small dual clock fifo will help to read the sync pulse from clk1 domain into clk2 domain
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