Forum Discussion
Altera_Forum
Honored Contributor
9 years agoUnfortunately the system is composed by two different fpgas with 2 different clocks' sources because the fpgas are located on 2 independent boards. The sync pulses come from an external cpu (another board in the system).
I'd like the idea of PLL but i don't know how to implement it.... The simplest way for me in order to avoid heavy changes on alredy written code is acting on NCO inputs. Have you any ideas? Thanks