syncronize nco on different fpga

If you wish you can just use the pulse as reset and that may be enough as long as you want a simple design and anytime during running you may apply that reset if required.

You still need your clock enable @ 25KHz as your clock rate is 50MHz.

Now I expected the two clocks are from same source.If they are from different sources(unrelated) then you got some more work to do since phase and frequency drift will occur.

One method is to create a sort of PLL as follows:

one fpga(master) will need both clocks available. you run a counter on each clock that increments from zero on master clock and decrements on slave clock. Add them together.

If clocks are tied up then the sum will stay. If they are not tied up the sum will give you error and its sense.

You use that error to generate enable on master nco., based on modulo adder. for example you use 20 bit accumulator that increments/decrements by the error (will need some scaling).

If the master counter is faster you slow it down and vice versa by generating enable at accumulator overflow. for 70Hz sinusoid this method should be fine.