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So if you have a sync pulse then wait for it in each fpga and assuming they arrive at NCO at same time then both NCOs can be enabled together from zero phase. All you need is convert that sync pulse to high signal starting once sync pulse arrives.
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So i've to reset NCO at first pulse of sync and start to generate a clk-enable? How can i manage the problem of 2 different clock drift during time (50MHz 50PPM)?
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Then the two outputs will go to DACs I assume and again delay issues may arise which you can measure and adjust digitally to within your available clock resolution.
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Actually the NCO output is compared with triangular wave and a pwm for inverter is generated.
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