Synchronizing TXCVR & RXCVR

Hi:

I am using the Cy IV. I instantiated transceiver with Automatic synchronization . I see the pattern signals indicated the K28.5 coding correctly .. they came h9CBC, BCBC. I figured this happens sometimes after the RX reset is de-asserted.

So now the RX FSM knows the interface is good ( Ithink).

1- If the transmitter is up an running, when should it start sending real data

2- Since the FPGA FSM transmitter side is sending "something" on every clock cycle while the synchronization is detected by the RXCVR and after when does the transmitter start sending real data? How does the FPGA FSM know the beginng of real data vs the "filled data" that was sent until synchronization ocurrs? I assume at this point a protocol with beginning or frame or something needs to be detected as well and then every clock cycle is valid data until some kind of "end of frame"? (based on some type of protocol I assume)

2- In fig 1-23 the byte order is shown misaligned but the byte ordering block that follows should put the data back into the same byte ordering as the transmitter (correct?)

thank you