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Altera_Forum
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12 years ago

Synchronized clocks on MAX V CPLD

I am using a MAX V CPLD to drive a chain of serial ADCs. If I have multiple IO pins driven by the same internal clock signal, what might I expect for pin-to-pin clock skew?
Altera_Forum's avatar
Altera_Forum
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12 years ago

Can be hundreds of ps or a few ns, depending on the routing.

Are those I/O pins just copies of the clock signal or are they output of registers driven by the clock?

In any case, build a small project, compile it and see the TimeQuest report.