Honored Contributor
Honored Contributor100 MBy/s (1Gb/s) isn't your requirement, you said you needed 10Mbits/sec, which is comfortable speed for something similar to SPI. 1Gb/s / 100MBy/s and for you'd be looking at RMII / GMII / SGMII types of links or add a PHY and use Gb-ethernet, or just a simpler trivial LVDS implementation for a short board to board link.
For a half duplex link -- (add another in reverse if you want bidirectionality). You can just use one differential LVDS pair, transmit scrambled/encoded data at 20Mb/s and do fabric (not SERDES) based sampling and CDR at the remote end like the application notes for multiplexed LVDS say. Or send 2 differential pairs: (clk+, clk-), and (txd+, txd-), 4 wires + board-to-board GROUND, and don't worry about clock data recovery, just packet framing which could be as simple as NRZ UART mode or something like SDLC/HDLC or whatever if you prefer, nothing difficult at all. Or if you make the protocol take turns (either via a bus grant / direction line in hardware or a logic based multiple access token ring like scheme) you could share the same physical data (and optionally clock, unless multiplexed with the data) lines for bidirectional use halving the interconnect requirements at the cost of latency and bus sharing complexity. Other approaches might be to use the JTAG system or access the 2nd board's configuration data stream from the 1st board if you already share these connections and making use of them would be feasible to achieve your needs, it would conserve more interconnect resources and take better advantage of what you already have. You didn't say if the need was bidirectional, master/slave, one time only, or continuous transmission. Of course if the boards are on the same ethernet channel and you can inject a custom packet into that . . . --- Quote Start --- I'll have a think about SPI speed. Do you really think 100MBytes/sec is simple in hardware as I make that 800MHz. --- Quote End ---
