Suggestions for simple link between two FPGAs?

Yes, SPI should would nicely without using that much I/O.

SERDES would just be excessive for a mere 10Mby/s rate, unless you know you're going to use a XCVR equipped part, AND have an unused channel. Using a SERDES XCVR would be, to me, using "loads of interconnect" seeing as how you only have a few available in most devices, and the cost per XCVR is pretty high.

The alternatives to SPI could be doing something like LVDS which should work fine at that distance and data rate, though you'd use more I/O due to the differential signaling. If you wanted to you could use something like a RS-422 transceiver (which will get you 10 Mbit/s) to add some ESD protection and decouple the board to board link from the FPGAs' pins, though it would be overkill for a mere 6" run, it is cheap and relatively compact.

If isolation is a concern, there are optocouplers and capacitive or inductive monolitic coupler devices from the likes of TI, A/D, etc. that will couple general digital signals which could be SPI or RS422 pre-transceiver logic level signals, or any other protocol.

LVDS is basically made for sending high speed Gb/s level (just short of SERDES realm) multiplexed data over short board-to-board distances, with low EMI and good signal integrity which is why they use it in LCD panel to controller board links, and it can commonly run up near 1Gb/s so a mere 10Mb/s is no difficulty with it, and it does not require a SERDES, or, in fact, any difficult multiplexing of the parallel data bits at that slow rate. The only real concerns would be ESD and any power / protocol sequencing issues, and implementing the framing state machine, but there are app notes for that, or any simple ad hoc encoding solution would be fine without a clock or any ad hoc framing solution if you transmit the clock distinctly (not really a worry over 6" B-B @ 10Mb/s with a decent interconnect).