Forum Discussion
New ContributorSub -LVDS IO standard
Hello guys,
I really appreciate the your efforts.
From your suggestions, i could make the conclusion that to interface the sub LVDS i need to check the IO receiver standard specifically i need check the VICM range along with receiver swing range. Also we need to careful about choosing the DDR LVDS receiver speed as well.
Super ContributorHi,
if you read FPGA datasheets, you'll see that LVDS receivers of most FPGA series support Sub-LVDS level (Vicm=0.9V) with limited data rate, e.g. Cyclone 10 up to 700 MBPS. You didn't mention speed requirements but I guess that's sufficent for your application.
You also need Gigabit Transceivers to send out MIPI CSI-2. Cyclone 10 GX would be my first choice.
New Contributorhello there ,
Thank you very much for your response!
accept my apologies to not providing clock details , here are the clock details,
"Synchronous serial output with sub-LVDS levels
16 data lanes with 4 clock lanes (total of 20 lanes, 10 for even rows and 10 for odd rows)
data transfer rate: 1100 Mbps for maximum frame rate
DDR clock for synchronization at 550 MHz"
Could you please enlighten me little about selecting sub LVDS receiver
dont we need to check about differential voltage swing ? as i mentioned my data have output swing can be 0.262V to 0.54V
i went through different data available on google about subLVDS i can see there receiver input threshold are there could you please explain how they work ?
