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Altera_Forum's avatar
Altera_Forum
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8 years ago

Stuck on Fast QSPI

I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second). That seems like it should be po...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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1) Do the tools automatically account for the phase difference between CLK_FLASH and CLK_CORE?

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In my constrains I have included -phase option. So phase difference should be accounted.

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2) What is “set_false_path -to [get_ports FLASH_SCLK]” doing? I took that out and did not notice anything change.

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It prevents FLASH_SCLK from being analysed as data. By using this command only the FLASH_SCLK as data is cut off, but as a part of a clock path it will not be effected. In some cases timequest will treat your clock output as data port and you will see it in TimeQuest unconstrained paths report list. set_false_path command removes it from there.