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Honored Contributor
Honored ContributorStuck on Fast QSPI
I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second). That seems like it should be po...
Altera_ForumHonored Contributor
Honored ContributorThank you, this looks great. I had thought that the input delay constraint clock needed to be the actual clock to the input registers. It really helps to have an example like this to see how to work around that.
Similarly, I thought the output delay constraint clock needed to be the output register clock (or physically connected to it, at least). With the way that you have it written: 1) Do the tools automatically account for the phase difference between CLK_FLASH and CLK_CORE? 2) What is “set_false_path -to [get_ports FLASH_SCLK]” doing? I took that out and did not notice anything change. Also, how did you come up with the specific phase shift amount? This is probably all pretty basic, but it is my first time working with phase-shifted copies of clocks.
