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The Tco of the QSPI part (6ns) is longer than the time from a falling edge to a rising edge (5ns). Why would moving to the 5ns window instead of the 10ns window help?
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Inverting output clock gives same window for input paths but you have to change your internal FPGA registers to be clocked on rising edge of clk98meg. It would be same window as you were getting by clocking your internal FPGA registers from negative edge see attached image. But by inverting clock on output you will avoid this confusion on negative edge clocked registers inside FPGA.
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TimeQuest is also telling me that adding a DDIO block to the clock path increases the FPGA’s clock output delay.
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Yes this is true. So I have modified your design and added second PLL to shift clock FLASH_SCLK. Phase shift is slightly less than 180 to meet timing requirements.
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