Honored Contributor
Honored ContributorI wrote my output constraints based on AN433. I used Figure 14 (Circuit with Common Data Clock and Output Clocks) without the DDR flops. Then I used the System-Centric output examples to set output delays. Timequest seems to be happy with that. There aren’t any failures reported on data output paths.
However, the data inputs are different. AN433 says it only constrains cases where clock and data are provided by the same device. That is not the case for data coming back from the QSPI part, since the QSPI part is not providing the clock. I wrote some input_delay constraints based on what made sense to me, but they are reporting failures by about 400ps in one of the corners (slow, 85C). Timequest shows that in the 10ns window, I am losing: 1) 6.21ns to QSPI device Tco and board delays 2) 3ns to FPGA clock output delay 3) 1.135ns to FPGA data input delay I do not know how to proceed from here. I already have fast input registers enabled, so I don’t see the data input delay getting any shorter. Is there a way to make the clock delay shorter?
