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Honored Contributor
Honored ContributorStuck on Fast QSPI
I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second). That seems like it should be po...
Altera_ForumHonored Contributor
Honored ContributorThere is a fairly good reference guide as to which timing constraints you need for Altera's Parallel Flash Loader (PFL) core available here:
https://www.altera.com/documentation/sss1411439280066.html#sss1411979414512 I acknowledge this isn't the quad memory device you're discussing. However, if you consider the clock and synchronous constraints it discusses it covers everything you need to consider for your application. Also use Altera's "an 433: constraining and analyzing source-synchronous interfaces (https://www.altera.com/en_us/pdfs/literature/an/an433.pdf)". This will confirm the exact syntax you need and discusses synchronous constraints more generically. Cheers, Alex
