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Luckily, there is no concurrent LVDS data that I need to transmit, other than a source LVDS clock from the FPGA. I just need to get a hold of data which is transmitted from the device I need to control.
The LVDS clock I generate gets passed into the device I'm trying to interface with, then back out alongside LVDS data on four other parallel lines. So, what I'll need to do is try and clock in the data based on a phase shifted version of the original clock I'm generating from the FPGA.
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Why use the original clock, when the device sends a clock with the data? The clock sent with the data will have the same process-voltage-temperature (PVT) variation as the data, so would be the more useful clock to use. If you need the data in the clock domain of the original clock, then since you know they are phase-locked, you can use a shallow FIFO to cross from the rx_data+rx_clock into the tx_clock domain.
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Hopefully that means that we're working with just source-synchronous data from the device and nothing more (Unless source-synchronous implies that devices on each end need to be configured for synchronous TX/RX).
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Since the two devices use a common clock, they are synchronous. However, the clocks can have a phase shift, and at high-frequencies, the pair of clocks may shift phase slightly with respect to each other.
Cheers,
Dave
Honored Contributor
