Struggling with LVDS.

Hi again, Dave.

Luckily, there is no concurrent LVDS data that I need to transmit, other than a source LVDS clock from the FPGA. I just need to get a hold of data which is transmitted from the device I need to control.

The LVDS clock I generate gets passed into the device I'm trying to interface with, then back out alongside LVDS data on four other parallel lines. So, what I'll need to do is try and clock in the data based on a phase shifted version of the original clock I'm generating from the FPGA. Hopefully that means that we're working with just source-synchronous data from the device and nothing more (Unless source-synchronous implies that devices on each end need to be configured for synchronous TX/RX).

Thanks for the resources. I'll look for examples of someone using the LVDS block for clock generation and that should be a good starting point. I'm sure all of this stuff is in the ALTDDIO documentation, I'm probably just not taking it all in!

Using a PLL to clock in the external data is a great idea, if it's supported.

You've been extremely helpful. Thank you.