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So, just to check, these ALTDDIO functions require an input clock. Is it possible to drive the clock for the component from an external LVDS signal?
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Unless the LVDS link is designed for clock-and-data recovery, the data leaving the FPGA and the data being capture at the other end of the LVDS link need to be synchronous.
When LVDS is used in a source synchronous mode, the LVDS data is sent with an LVDS clock. In that case, you also use an altddio to send a clock, data_l is zero and data_h is one, and so the serialized data is just a single-data-rate clock, however, it has a known timing relation to the data.
You can also use an external clock, but you'll need to take care to perform a timing analysis to check that you meet the timing requirements of the external device. You can use the TimeQuest timing analysis tool to get th e FPGA timing information (and the external device data sheet for its timing). If you cannot meet timing when using an external clock directly, you can route the external clock to a PLL internal to the FPGA (depending on the device) and phase-shift that clock to meet external timing.
Check out the TimeQuest users guide by Rysc on the Altera Wiki.
http://www.alterawiki.com/wiki/timequest Cheers,
Dave
Honored Contributor
