Struggling with LVDS.

To understand the component, think about what is happening; if the LVDS is clocking out data at double-data-rate, then you need double the data in at the clock rate, eg., lets say the clock is 100MHz, then data_l and data_h are inputs that change every 100MHz clock period, however, the dataout LVDS signal changes at 200Mbps, i.e., on both the rising and falling edges of the clocks.

Create a Modelsim simulation with the components you are trying to use. That always helps me visualize what is going on.

The Cyclone III devices do not have hard-IP serializers, only DDR registers, so using the altddio component and defining the pin standard as LVDS is adequate for what you want to do. The altlvds component would use logic cells to implement a serdes on the Cylone III, whereas on the Stratix series it uses a hard-IP block.

Cheers,

Dave