Structural net expression error

hi guys,

i have problem when run this code, which previously run without error. it's really weird.

REG FF is instantiated from Altera Megafunction.

any idea how to solve this? error file attached.

This my Code :

file:///C:/DOCUME%7E1/mshaari1/LOCALS%7E1/Temp/moz-screenshot.jpg //packet bit converter

//author : mohd farhan

//function : convert 28-bit packet formation. split to 14-bit msb and lsb data

//language : verilog hdl

module packetbitconverter (clk,rst,en,addr_in,data_in_l,data_in_m,cmd,q1,q2,q3,q4);

parameter n = 16;

parameter k = 14;

parameter m = 12;

input clk,rst,en;

input [1:0]cmd;

input [m-1:0]addr_in;

input [k-1:0]data_in_l;

input [k-1:0]data_in_m;

wire [n-1:0]header; //internal connection

wire [n-1:0]data_in_lsb;

wire [n-1:0]data_in_msb;

output reg[n-1:0]q1; //header output

output reg[n-1:0]q2; //output for data_in_m

output reg[n-1:0]q3; //output for data_in_l

output reg[n-1:0]q4 = 0; //output q4 is always 0

//for addr_in, the coordinate is set in req unit, and will be appended with flit_type(2bit), cmd(2bit) here.

//start_packet,flit_type 2 bits = 11 cmd 2 bit, addr_in 12 bit

assign header = {2'b11,cmd,addr_in};

assign data_in_msb = {2'b01,data_in_m}; //concatenation. total bit 16

assign data_in_lsb = {2'b01,data_in_l};

reg_ff reg_ff_inst (

.clock ( clk ),

.data ( header ),

.enable ( en ),

.sclr ( rst),

.q (q1)

);

reg_ff reg_ff_inst2 (

.clock ( clk ),

.data (data_in_msb ),

.enable ( en ),

.sclr ( rst),

.q (q2)

);

reg_ff reg_ff_inst3 (

.clock ( clk ),

.data ( data_in_lsb ),

.enable ( en ),

.sclr ( rst),

.q (q3)

);

endmodule