StratixII GX: s2gxBasic - Reset Control and Power Down

Hello,

I would like to understand, where the difference between the maximum and minimum delay of 2.8ns comes from. I would like to ask for some more details, than it "is the maximum skew allowed on reset/powerdown ports" stated in the documentation. Actually, this requirement disallow me to succeed the timing closure of my design.

I have some doubts whether the constraints (suggested by the "Stratix II GX Device Handbook, Volume 2", page 2-224) make sense. Let assume a one uses two transceivers in the RX mode. Each receiver has independent reset signal: the res1 and the res2 which enters the digitalrest1 and the digitalreset2 ports of the respective transceiver blocks. Moreover, remove of each res* signal is synchronized with the independent clk1 and clk2 (signals pass through synchronizers). In principle clk1 and clk2 could come from RxClock of the receivers, however it's not required by the specification (is it ?)

Does it make sense to constrain separately the path res1 and res2 ? Since ie. clk1 may be completely asynchronous to the clock driving internally transceiver1, the constraint seems to be useless in prospect of the Recovery/Removal analysis, because this can't be performed (asynchronous source and destination clock).

I can imagine it's crucial when two transceivers work in a tandem (reset should be removed at the same clock cycle to assure consistency). However, according to my understanding, the digitalrests of all receivers should be grouped then and have the same max and min delay. Nevertheless the documentation allows to have independent values for every receiver, provided the difference max-min is less than 2.8ns.

I would be grateful for clarification. Thank you in advance.