StratixI maximum input current

But how much is the maximum input current for an input pin of the FPGA ? 25mA or 40mA?

And at pag 184 of stratix handbook there is this note:

(3)Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than

100 mA and periods shorter than 20 ns, or overshoot to the voltage shown in Table 4–9, based on input duty cycle

for input currents less than 100 ma. The overshoot is dependent upon duty cycle of the signal. The DC case is

equivalent to 100% duty cycle

It means that a current of 100mA is acceptable for short period?

I am assuming that the clamping voltage is 3.3 V+ 0.7 V = 4 V is this correct?

Thank you in advance