Stratix10MX, triple speed ethernet LVDS IO

Hi John,

Thanks for sharing the design file. Pls see my reply below.

1. For the fitter error

• I can't compile your design due to missing "nios_with_4_tse_sgmii_lvds_avalon_interface_camera_0.ip" file
  • Anyway, you are right on one IOPLL is available per one IO_BANK. You can refer to below user guide doc "figure 2"
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-gpio.pdf
  • For your selected S10 MX FPGA. the max available IOPLL is 15 as shown in attached pinout file pic. That means you can generate max of 15 TSE IP where one TSE IP will consume one IOPLL

1. For connecting 1G Ethernet to transceiver (XCVR) channel. Let me clarify again on below 2 options

• If you are using TSE IP - then user can only connect to LVDS IO, not XCVR channel
  • If you are using 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP - user can connect to XCVR channel
  • Example design of Multirate PHY IP is available in below link. The example design comes with both PHY and MAC together
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20073.pdf

Thanks.

Regards,

dlim