Stratix10 - register duplication on reset synchronization

Question

Hello.
I am using a stratix10 with Quartus 22.1-pro (rocky linux).my design uses an asynchronous reset that reaches most of the logic, resulting in very high tension.I have seen that some timing violations in some regions, when fixed, lead to other new timing violations on unrelated regions, therefore i imagine the tension at the reset line could help to relax timing.
However i was not able to duplicate the last register of my synchronization chain:. the automatic duplication ignored those registers (with no message). the "manual register duplication" assignment  (DUPLICATE_REGISTER) accepts only the "-to" parameter, and it was ignored (but not mentioned in the ignored assignments)
. i have not tried yet the DUPLICATE_HIERARCHY_DEPTH.. but i have the feeling it will not work either.
Is there a common approach to solve this?

Kind regards,
Rp

prob · Answer

Update: the "ignored assignments" report did not mention the rejected assignments but the duplication report did.
The assignments were rejected because of "synchronization register"

sstrell · Answer

Did you try max_fanout?
Also, it's possible Quartus is identifying this as a synchronization chain and trying to preserve it to prevent metastability.  I don't see why that would prevent duplicating the final register in the chain, but it's something to look at.
Also, since this is a hyperflex device, it's possible that hyper-retiming or some related attribute is preventing the duplication.  Do you have keep/preserve anywhere?

prob · Answer

I manage to have the duplication working , by adding a "pipeline chain" (with 4 stages) after the module containing the synchronization chain. But the duplication is really not smart: i got 1 duplicate with 1FF fanout and the other duplicate with 200FFs fanout.
So now i am trying with the DUPLICATE_HIERARCHY_DEPTH assignment applied to the last of the pipe-registers i have added (and value=2). But i am not able to see any duplication happening.

prob · Answer

Update:It seems that the issue on the missing hierarchical duplication is:"Register has secondary signals: rcv_s10_top|sys_clk_rst|ilkn_cd_rst_sync[2].rst_pipe|pipe_reg[3][0]".
I attach the post-synthesis technology map viewer for reference, generated with the following assignments active:set_instance_assignment -name GLOBAL_SIGNAL OFF -to rcv_s10_top|sys_clk_rst|ilkn_cd_rst_sync[*].rst_pipe|pipe_reg[*][0]set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH 2 -to rcv_s10_top|sys_clk_rst|ilkn_cd_rst_sync[*].rst_pipe|pipe_reg[3][0]
Somebody can tell me what is a secondary signal in this case? The asynchronous reset?

sstrell · Answer

The optimization user guide explains exactly why this is not working for you (can't have any secondary signals at all, probably because the feature uses hyper-registers): https://www.intel.com/content/www/us/en/docs/programmable/683641/22-3/automatic-register-duplication-hierarchical.html

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Stratix10 - register duplication on reset synchronization

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