Stratix V MLAB Byte Enable Issue

Never mind. I gave up with altdpram and simply wrote my own module with an inferred RAM. Works perfectly

/* 
 * I2C CSR Zero-Latency RAM 
 * ------------------------ 
 * 
 * This module provides inferred RAM logic with zero read latency 
 * and working byte enables. For some reason the altdpram instances 
 * are failing to use byte enables correctly. 
 * 
 */ 
  
module i2c_csr_ram_hw# ( 
    parameter DATA_WIDTH   = 32, 
    parameter BYTEEN_WIDTH = 4, 
    parameter ADDR_WIDTH   = 2 
) ( 
    input                         clock, 
         
    input       writeAddress, 
    input       writeByteEn, 
    input       writeData, 
    input                         writeEn, 
     
    input       readAddress, 
    output reg  readData 
); 
localparam MEM_WORDS = 1 << ADDR_WIDTH; 
localparam BYTE_WIDTH = DATA_WIDTH / BYTEEN_WIDTH; 
//For simplicity the memory for each byte is instantiated separately. 
genvar i; 
generate for (i = 0; i < BYTEEN_WIDTH; i = i + 1) begin : ram_loop 
    //Offset into data word 
    localparam j = BYTE_WIDTH * i; 
    //Our memory for this byte 
    reg  memory ; 
    //Write port 
    always @ (posedge clock) begin 
        if (writeByteEn && writeEn) begin 
            //When this byte is enabled and we are performing a write 
            memory <= writeData; //Store this byte from the writeData word. 
        end 
    end 
     
    //Read port with zero latency 
    always @ * begin 
        readData <= memory; 
    end 
end endgenerate 
     
endmodule