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RBach6's avatar
RBach6
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7 years ago

Stratix IVGX (EP4SGX70HF35C3) PLL+SERDES issue

Hi, I am using an eval board from Texas Instruments (TSW1400evm). I am trying to implement altpll+altlvds_rx and running into an issue. Clock pin goes into pins AA7 and AA6 which are dedicated clock...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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7 years ago

Eventhough ADC interface use the DCLK , from the TIEVM design looks LVDS which is connect to ADC is using LVDS clock .I am looking into the RTL viwer , Here is the screen shot for your reference . If you would like to use the right / left pll kindly request you select the right bank pll for coressponding LVDS channel.

Also let me know how i can help you further to sort it out ?

Thank you ,

regards,

Sree

  • RBach6's avatar
    RBach6
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    7 years ago

    Hi Sree,

    not sure what are you looking at. TSW1400EVM calls the clock DCLK on the schematic which is mapped to clk_lvds_rx0_p in the code and it is on the pins AA7 and AA6 which is connected pll_R2. When I create the megafunction, it shows it has to be implemented in Left/Right PLL and it is fine without the altlvds_rx component. It maps to pll_R2. As soon as I add the serdes component, it complains about pll which drives non dpa-mode serdes is driven by an uncompensated input. I am not sure how to fix this error and what is causing it

    Ramakrishna