Stratix IVGX (EP4SGX70HF35C3) PLL+SERDES issue

​Hi Sree,

if you look at the schematic, dclk from adc goes to pins AA7 and AA6 which comes from pins 56 and 58 from the ADC interface (J3A). In the altpll megafunction, it comes up with the suggestion for Left/Right pll and I compiled the design and this translates to PLL_R2. I haven't changed any pin mapping. If I don't add altlvds_rx, the design compiles and maps to the same location. When I include the altlvds_tx with the clock coming from altpll, it gives the errors I included in the original message

Ramakrishna