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Honored Contributor
Honored ContributorStratix IV Hold Violations....
... between register A and B. Both Registers are fed by a Global Clock. Source Register and Latch Register are in adjacent labs. The problem seems to be coming from Register A being of type "ALM R...
Altera_ForumHonored Contributor
Honored Contributor-- Combinational ALUTs 252,121 / 424,960 ( 59 % )
ALUTs Used 267,397 / 424,960 ( 63 % ) Memory ALUTs 7,522 / 212,480 ( 4 % ) Dedicated logic registers 292,171 / 424,960 ( 69 % ) LUT_REGs 7,754 / 424,960 ( 2 % ) It doesn't seem that they are being called as a matter of last resort. Above report is from the fitter. The synthesis reports shows 0 so the fitter is mapping them to the LUT_REG. To me, it seems the fitter is making a bad decision about inferring these. When I tell the tool to fix the hold times, I see a lot of very bad setup violations (500 ps to 1000 ps). When I tell the tool to NOT fix hold I see no setup violations (positive setup of a 200+ ps). If the tool would not map the logic to the LUT_REG it appears that my hold violations would go away. I miss the old days when hold time was guaranteed by device construction (delay from LUT/REG to LUT/REG was guaranteed when source and destination where in the same clock domain).
