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"Will these separate systems use a common transceiver reference clock?"
They would be common frequency, but not a single source.
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Ok.
I'm not sure if you have used transceivers before, so I'll add a word of caution. The receiver PLLs will need to lock to a local reference clock (lock-to-reference, or LTR mode), and then when the received data has enough transitions, it can lock-to-data (LTD). The reference oscillators used at each end of the link need to be 'the same' frequency, within some specified frequency tolerance (specified in the Stratix IV handbook somewhere). You'll want to make sure your oscillators meet that requirement. In the link tests I've been doing, I've been using a common reference, so I can't comment on what you need for your mode of operation.
You mentioned that your data will be 'bursty', so there should be no issue with the receiver-end of the link being overrun by a transmitter-end sending too much data.
Cheers,
Dave
Honored Contributor
