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Honored Contributor
11 years agoYou're correct
The Explantion is found in StratixIV HandBook, Chapter 5 "Clock Networks and PLLs in Stratix IV Devices", page 5-14: "Clock Control Block ... The mapping between the input clock pins, PLL counter outputs, and clock control block inputs is as follows: - inclk[0] and inclk[1]- can be fed by any of the four dedicated clock pins on the same side of the stratix iv device- inclk[2] - can be fed by PLL counters C0 and C2 from the two center PLLs on the same side of the Stratix IV device - inclk[3] - can be fed by PLL counters C1 and C3 from the two center PLLs on the same side of the Stratix IV device ..."