Stratix III reconfigurable PLL switched clocks

Hello,

In Stratix III FPGA, reconfigurable PLL (top/bottom PLL), I want to ensure the output clocks have low jitter. How do I go about to set up any parameter to control this? I've noticed there's a parameter call VCO counter and it has something to do with bandwidth setting that affect the output clock jitter. Is this the right parameter to look at for controlling output clock jitter?

Please advise on how to control/setup the PLL's jitter for output clocks....

Thank you....Daven