Stratix III reconfigurable PLL switched clocks

Hello daven,

Sorry for my late reply, I didn't got noticed of this reply by mail earlier.

It has been some time when I used dynamic PLL configuration, but I let you know what I know and remember.

First of all, your formula seems correct. What we did to have all correct settings for a dynamic reconfiguration was not calculating them let Quartus calculate/decide them. We scripted with tcl a tool that changed the input files with the desired frequency for all phase shifted clocks, compile the project, read the reports for the PLL settings and copied them into a table. This was done for all 300 or so frequencies we needed. Then you are sure that all settings are feasible.

The resulted table with all needed frequencies and all phase shifted clocks was then loaded into the software (CPU aside from the FPGA) that decided which frequency to use. The CPU then sends the data to the FPGA via a wrapper interface around the altpll_reconfig instance. The counter_type and counter_param is used to tell which setting from which clock you want to change, you just use the binary code from the datasheet (http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf).

Hope thiss helps!

Kind regards,

JBC