--- Quote Start ---
Setting the option "Preserve PLL Counter Order logic" solved the problem. I must have overlooked this.
--- Quote End ---
Hello JBC,
I am a newbie at PLL dynamic reconfiguration. I was searching the Forum and came across your message. Please, if you could give me some tips....
1. Summary of task:
I have a Stratix III FPGA and want to dynamically adjust all the ouputs (C0 - C9) of the PLL1 (Top/Bottom) to the same desired frequency (for example change the clock outputs C[9:0] from 1 MHz to C[9:0] 200 MHz.)
Note: These clocks are also hard coded during ALTPLL1 instance setup to have 45 degrees phase shifted from each other, example C0 = 0 degree, C1 = 45 degress, C2 = 90 degree....)
I believe the formula to change the frequency is Fout = Fin x (M/(NxC); Fout = Output Frequency, Fin = Input Frequency (in this case = 10 MHz), M = feedback multiplier counter, N = pre-divider counter, C = post devidiver counter.
2. Problem:
I have so far set up two instances ALTPLL_RECONFIG and ALTPLL1 using the MegaWizard_PlugIn Manager. For setting up the desired output frequency, I need to set up the counter_type[3:0] and the counter_param[2:0] and I don't quite understand what these two parameters are about and how to select them properly. There are set up for counter's high count, low count...What do they mean?
I also noticed that in the data specs for counter_type, it does not list binary code for the post divider counter C! The data specs/app notes do not say much. Can you provide some explaination....Thank you DaveN
Note: In my design I am not using .mif file/external ROM to reconfigure the output clocks. The control signals/data to reconfigure the output clocks come from a state machine.
Honored Contributor
