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Altera_Forum's avatar
Altera_Forum
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14 years ago

Stratix III power-up problem

Due to powersave requirements, my board has the ability to switch the FPGA / DDR memory / sensor part off, if not used for a certain time. I consider this similar to a hot-socketing behaviour, which ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

After having investigated all my fife boards, I observe:

  • None of the two dips occur on the board with an EP3SL50 device (I have only one)

  • The first dip (at the end of 3V3 ramp up) occurs on all 4 EP3SL70 boards

  • The second dip (during 2V5 and lower voltages ramp up) occurs on only one of the EP3SL70 boards.

Is this an EP3SL70 mis-behaviour?