Forum Discussion

Honored Contributor

17 years ago

Stratix III final timing specs

I am designing a Stratix III EP3SE110 FPGA with Quartus version 8.1. I have been using the Stratix III user guide dated October, 2008 (volume 1 is version 1.6 and volume 2 is version 1.8, for Quartu...

Altera_Forum

Honored Contributor

17 years ago

Can you send me the link to download "Stratix III user guide"

Forum Discussion

Stratix III final timing specs

Recent Discussions

Timing Slacks inside Altera IP

Part Status request

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger