Stratix III final timing specs

I am designing a Stratix III EP3SE110 FPGA with Quartus version 8.1. I have been using the Stratix III user guide dated October, 2008 (volume 1 is version 1.6 and volume 2 is version 1.8, for Quartus 8.1). I just downloaded the new Stratix III user guide dated February, 2009 (volume 1 is version 1.7 and volume 2 is version 1.9, both for Quartus 9.0).

The I/O timing model status for the EP3SE110 is listed as "final" in both versions of these Stratix III user guides. However, many of the I/O timing specs have changed in the new user guide, some very dramatically. For example, consider the "EP3SE110 column pin output timing parameters" (table 1-132 in the Oct-2008 data sheet and table 1-125 in the Feb-2009 data sheet). For 1.5V HSTL class 1 outputs, 8mA drive, output clocked by GCLK PLL, -I3 speed grade, the Tco for the fast model changed from 3.704ns to 1.222ns, and the Tco for the slow model (-I3) changed from 5.699ns to 1.962ns.

My questions are:

1. Why did the timing specs change from one data sheet to the other if the timing data status is "final" in both data sheets? Is one of them a typo and which ones are correct?

2. Do the timing parameters used for timing analysis in Quartus reflect the numbers shown in the data sheet, for the Quartus version corresponding to the version of the data sheet?

3. Does Quartus 8.1 have the latest "final" timing data for the EP3SE110 device? Is the timing data for the EP3SE110 the same in Quartus 8.1 and 9.0, or do I need to upgrade to Quartus 9.0 in order to do timing analysis with the latest up-to-date timing data?