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Altera_Forum
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17 years ago

Stratix III Fast PLL I/O issue

Hi there, I'm currently developing a design for a Stratix III using the altlvds receiver and transmitter with internal, shared PLLs. Synthesis in Quartus 8.1 works fine but the fitter throws th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The problem seems to be solved by adding one additional clk buffer (altclkctrl from megawizard) between the input clock and all other units.

lestard