Stratix-III DDR2 SDRAM memory pin error message.

Hello,

I'm using a Stratix-III development kit (DK-DEV-3SL150N) and trying to use the DDR2 SDRAM (U17) to work

in my own FPGA configuration. I've verified that I can access the memory using the tutorial that came with

the kit. I'd like to understand how all this works. Anyway, I'm getting the below error message during the

fitter phase.

Error:Bidirectional pin DDR2_DEVA_CK_N with a pseudo-differential I/O standard must use the output enable control signal on the output buffer.

I've had a look at the pin definitions in the development kit (that worked) and mine and the look the same. Where

in the assignment editor do I make this assignment for the "output enable control signal"? Or am I on the wrong path?

Please advise, thanks in advance,