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Honored Contributor
Honored ContributorStratix II: Input clock from an external PLL
Hi everyone! I have a problem with my synthesis: I usually use FPGA's internal PLL to drive my RTL, using CLK1.....15p/n to drive the inclk PLL input, but now I need to drive the clock path of...
Altera_ForumHonored Contributor
Honored ContributorI already don't understand the clock buffer point. A FPGA global clock tree can be setup by using a dedicated clock input in your design. You don't have to care for clock buffers that are inserted by Quartus automaticly. It doesn't matter, if the clock source is a crystal or some kind of PLL. If there are other problems implied with your design, you apparently failed in clarifying them.
