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Altera_Forum
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18 years ago

Stratix II: Input clock from an external PLL

Hi everyone! I have a problem with my synthesis: I usually use FPGA's internal PLL to drive my RTL, using CLK1.....15p/n to drive the inclk PLL input, but now I need to drive the clock path of...
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Altera_Forum
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18 years ago

There is no inherent problem with using an external clock source. What exactly is it that doesn't work?

If it appears to compile correctly but does not operate as expected, it could be a timing related problem. You must specify the clock settings manually, as Quartus can no longer infer these from the PLL instantiation. Also, IO timings will be affected.