Stratix II - Asynchronous RAM Memory

How big is the cache? I think doing it in triplicate is the easiest method, assuming there's enough memory. If you need more, then you need to develop some interface. (Note that you already had difficulties if asynchronous RAMs were available. No RAMs have 3 read ports, so you would need arbitration logic that handles who is reading the memory, and that arbitration logic needs to work across independent clock domains, which means handshaking or some other cross-domain logic.) So I don't think asynchronous memory was going to be very easy either.

Being synchronous, you can do reads from two of the domains(since you can have two synchronous read ports), and the third domain would need to have its read requests go through a DCFIFO into one of the existing two domains, and then the read data go back through a DCFIFO.

And of course thinking about it, you wouldn't need three copies of your RAM for the more trivial solution, you would need 2.

I assume you also disable all reads while doing writes, or have some way of ensuring you're writing to a location not being read on another clock domain?