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Altera_Forum's avatar
Altera_Forum
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17 years ago

Stratix 2 Configuration

Hello,

I have a Stratix2 being configured from an EPC8 and on most boards everything is fine. But I have a couple of boards that won't configure. The interesting bit to me is that while monitoring the nSTATUS I've noticed that the pulse width is much shorter than I would expect from the POR settings. On the good boards the nSTATUS is low for greater than 200msec; but on the boards that won't configure the low pulse width is less than 50usec. In each case the DCLK starts after the rising edge of nSTATUS.

I have the POR of the FPGA set at 12msec and the POR on the EPC8 set at 100msec

Any thoughts?

Thank you,

Rob

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Read through chapter 7 of the Stratix Device Handbook, Volume 2, regarding VCCPD and VCCSEL. You can have problems with POR if the VCCPD and VCCSEL isn't ideal. I think this was covered in an errata item.