New Contributor
New ContributorHello Rashmi,
1. Yes, we are using the PHYlite interface to DDR4; correct, we process the calibration by ourselves. We used Arria 10 in our last project, we used PHY Lite on Arria 10 as well, we just don't know why it is so weird on Stratix 10.
2. We use test socket to interface the DDR4.
3. Yes, we see the same issue using v20.2, we have finished our PCB design, the IO pins are all populated in Bank 3.
4. It is not related to the speed, we are running 1600Mbps, we are trying to communicate with the PHY Lite on the avalon bus, but we failed to read the basic information from the PHY Lite on the addresss 0x05000024.
5. We are currently using v20.2.
6. We did the simulation on ModelSim-Intel, the waitrequest and valid signals are correct, but the readdata is 0.
Thanks,
Samson
New ContributorHello Rashmi,
I have discussed with my team, we hope to get a simple reference design which has a correct response on the avalon bus with the PHY Lite, and then we may modify our design on that and we may see the RTL to check what is wrong with our logic.
We received a simple example from Altera FAE Nur Aida before, today I modified this example to read the address 0x05000024 on our test board, but the data is still 0.
I have attached the archive project here, this is a very simple design, would you please help us to take a look on it? There is a signal tap file called "aida_file_v2.stp", would you please help to take a look to see if there is anything wrong?
The PHY Lite is very important to us, we have been stuck on this of a couple of months.
Thanks,
Samson
