New Contributor
Occasional ContributorHi Samson,
Can you please confirm on the below questions:
Customer design:
Interface frequency is 1200MHz, Quarter clock rate, LVDS with on-chip termination, SSTL-12
1st Phylite instance: output DDR, 4 groups and different pins per each group
2nd Phylite instance: output DDR, 1 group and 4pins
3rd Phylite instance: output DDR, 4 groups with different pins per each group
4th Phylite instance: output DDR, 3 groups with 9 pins per each group
5th,6th,7th Phylite instances: output DDR, 2 groups with 9 pins per each group
1. You are using the PHYlite interface to DDR4, they write their own code in Avalon-mm debug in order to process the calibration?
2. To understand the design background, is the customer using all the Phylite groups to communicate with a DDR4 by using a multiple of cables to connect them?
3. How are you trying to use a new version of Quartus, still can see the identical issue? Did you try to instantiate other IO bank location instead of Bank 3 (Bank 3B, 3K, 3L, 3J, 3I, 3D and 3C)?
4. Instead of 1200MHz interface frequency, did you reduce the interface frequency? If yes, did you face the same issue, and please share the result.
5. I proposed you to uses a new Quartus and pending your update for this, If this is the root cause, it will be fixed in Quartus 20.1.
6. If you got chance to simulate your design can you share the simulation result of this?
Thanks,
Rashmi
New ContributorHello Rashmi,
1. Yes, we are using the PHYlite interface to DDR4; correct, we process the calibration by ourselves. We used Arria 10 in our last project, we used PHY Lite on Arria 10 as well, we just don't know why it is so weird on Stratix 10.
2. We use test socket to interface the DDR4.
3. Yes, we see the same issue using v20.2, we have finished our PCB design, the IO pins are all populated in Bank 3.
4. It is not related to the speed, we are running 1600Mbps, we are trying to communicate with the PHY Lite on the avalon bus, but we failed to read the basic information from the PHY Lite on the addresss 0x05000024.
5. We are currently using v20.2.
6. We did the simulation on ModelSim-Intel, the waitrequest and valid signals are correct, but the readdata is 0.
Thanks,
Samson
New ContributorHello Rashmi,
I have discussed with my team, we hope to get a simple reference design which has a correct response on the avalon bus with the PHY Lite, and then we may modify our design on that and we may see the RTL to check what is wrong with our logic.
We received a simple example from Altera FAE Nur Aida before, today I modified this example to read the address 0x05000024 on our test board, but the data is still 0.
I have attached the archive project here, this is a very simple design, would you please help us to take a look on it? There is a signal tap file called "aida_file_v2.stp", would you please help to take a look to see if there is anything wrong?
The PHY Lite is very important to us, we have been stuck on this of a couple of months.
Thanks,
Samson
