Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Samson,

Can you please confirm on the below questions:

Customer design:
Interface frequency is 1200MHz, Quarter clock rate, LVDS with on-chip termination, SSTL-12
1st Phylite instance: output DDR, 4 groups and different pins per each group
2nd Phylite instance: output DDR, 1 group and 4pins
3rd Phylite instance: output DDR, 4 groups with different pins per each group
4th Phylite instance: output DDR, 3 groups with 9 pins per each group
5th,6th,7th Phylite instances: output DDR, 2 groups with 9 pins per each group

1. You are using the PHYlite interface to DDR4, they write their own code in Avalon-mm debug in order to process the calibration?
2. To understand the design background, is the customer using all the Phylite groups to communicate with a DDR4 by using a multiple of cables to connect them?
3. How are you trying to use a new version of Quartus, still can see the identical issue? Did you try to instantiate other IO bank location instead of Bank 3 (Bank 3B, 3K, 3L, 3J, 3I, 3D and 3C)?
4. Instead of 1200MHz interface frequency, did you reduce the interface frequency? If yes, did you face the same issue, and please share the result.

5. I proposed you to uses a new Quartus and pending your update for this, If this is the root cause, it will be fixed in Quartus 20.1.

6. If you got chance to simulate your design can you share the simulation result of this?

Thanks,

Rashmi