Stratix 10 PCI Express Avalon®-MM DMA Reference Design. Interrupt generation.

Good day! Thanks for your attempt to help.

Perhaps my first question was not read carefully.

Let's go first.

I am developing a system (PCIExpress endpoint) based on a Stratix 10 board. This card contains a PCI Express interface. To read and write data to the board, I independently develop a driver for the Windows operating system. I built the system using Quartus Platform Designer. System Contents is shown in the figure. With a driver and BAR0 register, I control reads and writes from the board via DMA. Also, if necessary, through BAR4 I carry out simple read and write operations in on-chip memory.

SYSTEM CONTENTS

When my algorithms work

I need to generate custom interrupts. For this I use the rxm_irq_i{15:0} interface. When a pulse is applied to any of these inputs, interrupt registration does not occur. From the descriptions of the AN 829 User guide and the Intel Stratix10 Avalon - MM Interface for PCI Express Solutions User Guide, I realized that I need to enable interrupts through the Avalon-MM to PCIe Interrupt Enable Register .

my question to you is how to access this register through driver in windows ? how to correctly translate the address in accordance with the system contents shown in the figure? or should I implement logic inside the FPGA? without the participation of the host, will provide access to this register through the CRA interface?

Thanks for your reply. I hope that this time you understand the question.

Regards